【Apple】Senior Design Verification Engineer (Japan Design Center)
仕事内容
Description
• Construction of verification environment by using Verilog, SystemVerilog.
• Designing test plan for verification.
• Coding test scenarios, assertion and debugging for Digital Design.
応募資格(必須経験など)
Key Qualifications
• Typically requires a minimum of 5 years of experience in SystemVerilog or the other verification language.
• Hands-on experience of constrained random verification environments.
• Hands-on experience of Assertion Based Verification.
• Basic design background in support of verification results analysis.
• Knowledge with Object Oriented Programming.
• Being able to read and write in English (spoken English is not mandatory)
Education & Experience
BSEE/MSEE required
給与
当社規定による
業界
IT・エンジニア